Zynq-7000 Partial Reconfiguration Reference Design 14.2
Table of Contents


1 Introduction

This tutorial shows how to develop a Partial Reconfiguration (PR) design for the Zynq-7000 AP SoC using the Xilinx Platform Studio (XPS), Software Development Kit (SDK), and PlanAhead design tools. It complements application note XAPP1159 [7] which focuses on conceptual aspects of the PR flow and Zynq architecture specific design considerations.

1.1 Design Overview

The PR reference design is built on top of the ZC702 Base Targeted Reference Design (TRD) [1], an embedded video processing application that demonstrates how it is best to separate control and data processing functions. In this example a compute-intensive video filtering algorithm is moved from the Processing System (PS) onto a hardware accelerator in Programmable Logic (PL). The video filter IP core demonstrated in the ZC702 Base TRD is a Sobel filter configured with edge detection coefficients which has been generated using the High-Level Synthesis tool Vivado HLS. For this reference design, a second video filter IP core (Sepia filter) was generated again using Vivado HLS. The provided reference design demonstrates how to use software-controlled Partial Reconfiguration (PR) to dynamically reconfigure part of the PL with the desired video filter IP core and observe the video output on a monitor.

1.2 Requirements



  • ZC702 Evaluation Kit to run the PR reference design in hardware.
  • Monitor with HDMI or DVI port that supports 1080p60 video resolution.
  • Avnet FMC-IMAGEON module and external video source that provides 1080p60 video input over HDMI (optional).
  • USB hub, USB mouse, and USB keyboard (only required when using Linux boot image).


  • Xilinx Vivado HLS: A 30-day evaluation license can be generated after registering a Xilinx account.
  • Xilinx ISE Design Suite System Edition: A 30-day evaluation license can be generated after registering a Xilinx account.
  • Xilinx Partial Reconfiguration is a product inside the ISE Design Suite that requires a license. 30-day evaluation licenses are available through the Xilinx University Program (XUP).
  • Xilinx IP evaluation licenses for the Video Timing Controller and Chroma Resampler IP cores can be ordered online.
  • Xylon logiCVC-ML is shipped as evaluation IP core that does not require a license. License options are listed on the Xylon logiCVC-ML product site.
    Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. The pre-generated netlists are built from this evaluation IP core so the user can implement the design without having to purchase a license. The pre-built bitfiles and boot images are built from a full logiCVC IP core and don't expire.

1.3 Directory Structure

Unzip the reference design archive file xapp1159.zip to a local directory. The directory structure is:

  • zc702_pr_rd — Top-level directory
    • doc — Readme file
    • hw — Hardware sources
      • base_trd_prj — Pre-configured Base TRD PlanAhead project
      • hls_sepia_prj — Sepia filter Vivado HLS project
      • hls_sobel_prj — Sobel filter Vivado HLS project
      • pr_prj — Pre-configured PR PlanAhead project
    • sd — SD card images
      • linux — Linux boot image, kernel, devicetree, ramdisk, executables, partial binaries
      • standalone — Standalone boot image, partial binaries
    • sw — Software sources
      • boot — Zynq boot image sources
        • linux — Linux boot image sources
        • standalone — Standalone boot image sources
      • patch — Linux kernel patch
      • repo — SDK standalone user repository
        • drivers — SDK standalone user drivers
        • sw_services — SDK standalone user software services
      • workspace — SDK workspace/projects
        • filter_cmd — Linux command line software application
        • filter_qt — Linux Qt-GUI software application
        • filter_std — Standalone software application
        • hw_platform — Hardware platform information
        • standalone_bsp — Bare-metal board support package
        • zynq_fsbl — First stage boot loader

2 Vivado HLS Flow

Vivado HLS provides a tool and methodology for migrating algorithms coded in C, C++ or System-C from the Zynq PS onto the PL by generating RTL code. The Sobel filter IP core used in the Zynq Base TRD was generated using this approach. Similarly, the Sepia filter IP core can be generated based on the provided C-algorithm and Vivado HLS project. The following tutorial is based on [6] and shows how to implement the Sobel filter HLS project — the same methodology can be used for the Sepia filter HLS project.

Shortcut: Pre-generated Sobel and Sepia filter IP cores are available at zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_prj/pcores/sepia_filter_top_v1_02_b and zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_prj/pcores/sobel_filter_top_v1_02_b.

2.1 Synthesizing the HLS Design

2.2 Exporting the RTL as EDK Pcore

Repeat steps 2.1 and 2.2 for the Sepia filter HLS project located at zynq_pr_rd/hw/hls_sepia_prj.

3 PlanAhead Base TRD Flow

The Base TRD hardware design is a PlanAhead project with an embedded XPS project. The default video filter used in the design is a Sobel filter. First you will synthesize the Base TRD with the Sobel filter using PlanAhead. Then, you will replace the Sobel filter with a Sepia filter in XPS and re-run synthesis. The generated netlists will be used as starting point for the PlanAhead PR project (see Section 4). Finally, you will export the hardware platform information so it can be imported into SDK at a later point (see Section 6.1).

Shortcut: Pre-generated netlists are available inside the PlanAhead PR project zynq_pr_rd/hw/pr_prj. A pre-configured Hardware Platform Specification is available at zynq_pr_rd/sw/workspace/hw_platform.

3.1 Synthesizing the Design

3.2 Replacing the Filter and Re-Synthesizing the Design

3.3 Exporting the Hardware Platform Specification

4 PlanAhead Partial Reconfiguration Design Flow

Based on the synthesized netlists from the Base TRD hardware design, you will use the PlanAhead tool to create a reconfigurable partition, floorplan the design, add reconfigurable modules, run the implementation tools, and generate full and partial bitstreams. The promgen tool is used to convert the partial bitstreams to binary format so they can be used by the software application to configure the PL through the PCAP port.

Shortcut 1: A pre-built full bitstream (sobel configuration) is available at zynq_pr_rd/sw/boot/*/system.bit. Partial Sobel and Sepia bitstreams are available at zynq_pr_rd/sd/*/sepia.bin and zynq_pr_rd/sd/*/sobel.bin.

Shortcut 2: A pre-configured PlanAhead PR project is available at zynq_pr_rd/hw/pr_proj. When using this project, only the last two steps in the PR flow — implementation and bitstream generation — need to be run (see tutorial below).

Alternatively, complete Sections 4.1 through 4.9 for the full PR design flow tutorial.

4.1 Creating a PR Project and Importing the Generated Netlists

4.2 Defining a Reconfigurable Partition

4.3 Adding a Reconfigurable Module

4.4 Floorplanning the Reconfigurable Partition

4.5 Creating, Implementing, and Promoting the Sobel Configuration

4.6 Creating and Implementing the Sepia Configuration

4.7 Running the Verify Configuration Utility

4.8 Generating Full and Partial Bitstreams

4.9 Converting Partial Bitstreams to Binary Format

5 Linux Components

This section describes how to build Linux specific components i.e. the second stage boot loader u-boot, the Linux kernel image and device tree blob, and the Linux root file system. To complete this section, you are required to have a Linux development PC with the ARM GNU cross compile tool chain and the Git tool installed. Make sure you have your PATH and CROSS_COMPILE environment variables set correctly. You can use the corkscrew tool if you are having difficulties accessing Xilinx git repositories from behind a firewall.

5.1 Building the u-boot Second Stage Boot Loader

This section explains how to download the sources, configure, and build the u-boot second stage boot loader. For additional information, refer to the Xilinx Zynq u-boot wiki.

Shortcut: A pre-compiled u-boot executable is available at (zynq_pr_rd/sw/boot/linux/u-boot).

5.2 Building the Linux Kernel Image and Device Tree Blob

This section explains how to download the sources, configure, patch, and build the Linux kernel image and the device tree blob. For additional information, refer to the Xilinx Zynq Linux wiki.

Linux Kernel Image

Shortcut: A pre-compiled Linux kernel image is available at zynq_pr_rd/sd/linux/zImage.

Linux Device Tree Blob

Shortcut: A pre-compiled Linux device tree blob is available at zynq_pr_rd/sd/linux/devicetree.dtb.

5.3 Building the Linux Root File System

For instructions on how to build the Zynq Root File System, please refer to the Xilinx Zynq Root File System Creation wiki.

Shortcut: A pre-built ramdisk image is available at zynq_pr_rd/sd/linux/ramdisk8M.image.gz.

At the end of the etc/init.d/rcS script, a hook was added to execute a customized user script named init.sh. Our implementation of this script is located at zynq_pr_rd/sd/linux/init.sh and takes care of the following design specific initialization:

  • Mount the cross-compiled Qt/Qwt libraries image file (located at zynq_pr_rd/sd/linux/qt_lib.img)
  • Create Xilinx VDMA device node
  • Create Xilinx filter device node
  • Auto-start the Qt GUI based software application after boot-up

To remove the auto-start feature of the Qt application, simply comment the line ./run_sobel.sh -qt inside zynq_pr_rd/sd/linux/init.sh.

6 SDK Flow

This section describes how to use SDK to compile the standalone and Linux based software applications that control the video data path and the dynamic partial reconfiguration. You will also learn how to compile the First Stage Boot Loader (FSBL) and how to create a standalone or Linux Zynq boot image. For detailed information on SDK, the Zynq boot image format and boot process, refer to [4].

6.1 Creating a Hardware Platform Specification

The Hardware Platform Specification is obtained by running PlanAhead's Export to SDK tool (see Section 3.3). It generates an XML file (system.xml) that describes the hardware system including PS and PL components and C source files that initialize the PS (ps7_init.c/h). Follow the steps below to create a Hardware Platform Specification SDK project.

Shortcut: A pre-generated Hardware Platform Specification SDK project is available at zynq_pr_rd/sw/workspace/hw_platform.

6.2 Generating a Board Support Package

The Board Support Package (BSP) uses the information in the Hardware Platform Specification to assign drivers to the hardware components in the design. All PS drivers and most of the PL drivers are shipped with the SDK tool suite. Custom PL drivers and software services are provided as local user repository at zynq_pr_rd/sw/repo. The BSP is linked to the main application as a library.

Shortcut: A pre-generated Board Support Package SDK project is available at zynq_pr_rd/sw/workspace/standalone_bsp.

6.3 Compiling the Standalone Software Application

Compiling the standalone or bare-metal software application for Partial Reconfiguration requires Hardware Platform Specification (6.1) and BSP (6.2) SDK projects. This tutorial uses the pre-generated Hardware Platform and BSP SDK projects.

Shortcut: A pre-compiled executable is available at zynq_pr_rd/sw/boot/standalone/filter_std.elf.

6.4 Compiling the Linux Command Line Software Application

The command line Linux software application has no dependencies on any other SDK projects and can be compiled by itself.

Shortcut: A pre-compiled executable is available at zynq_pr_rd/sd/linux/filter_cmd.

6.5 Compiling the Linux Qt Software Application

The Qt Linux software application offers a GUI for navigation, built on top of the embedded Qt framework and the Qwt widget library. To complete this step, you are required to have a Linux development PC with the ARM GNU cross compile tool chain installed. For a detailed tutorial on how to build the Qt/Qwt libraries, refer to the Zynq Qt/Qwt Libraries - Build Instructions wiki. The Qt/Qwt libraries are required both, at run time and compile time. The pre-compiled Qt/Qwt image file is sufficient when executing the application on the Zynq platform. When compiling the application, in most cases you will need to recompile the Qt/Qwt libraries on your host platform since some of the generated Qt utilities are host-specific.

Shortcut: A pre-compiled Qt/Qwt libraries image file is available at zynq_pr_rd/sd/linux/qt_lib.img along with a pre-compiled executable at zynq_pr_rd/sd/linux/filter_qt. The executable also requires an image file, zynq_pr_rd/sd/linux/zynq.png, to load the Zynq splash screen when the application starts up.

6.6 Compiling the First Stage Boot Loader

Compiling the FSBL requires Hardware Platform Specification (6.1) and BSP (6.2) SDK projects. This tutorial uses the pre-generated Hardware Platform and BSP SDK projects. The FSBL SDK project has two build configurations, one named standalone, the other named linux. The linux configuration is a customized version of the standard Xilinx FSBL which adds the following functionality:

  • I2C initialization sequence for HDMI transmitter (ADV7511) on ZC702 base board
  • I2C FMC-IMAGEON daughter card detection sequence
  • I2C initialization sequence for HDMI receiver (ADV7611) on Avnet FMC-IMAGEON

In the standalone case, the corresponding initialization is done inside the application itself instead of the FSBL.

Shortcut: Pre-compiled FSBL executables are available at zynq_pr_rd/sw/boot/standalone/zynq_fsbl.elf and zynq_pr_rd/sw/boot/linux/zynq_fsbl.elf

6.7 Creating a Standalone Boot Image

Creating a standalone boot image requires the following components:

zynq_fsbl.elf FSBL - standalone configuration (6.6)
sobel.bit Full bitstream - sobel configuration (4.8)
filter_std.elf Standalone software application (6.3)

All required files to build the boot image are available at zynq_pr_rd/sw/boot/standalone.

Shortcut: A pre-generated standalone boot image is available at zynq_pr_rd/sd/standalone/BOOT.bin.

6.8 Creating a Linux Boot Image

Creating a Linux boot image requires the following components:

zynq_fsbl.elf FSBL - linux configuration (6.6)
sobel.bit Full bitstream - sobel configuration (4.8)
u-boot.elf u-boot - second stage boot loader (5.1)

All required files to build the boot image are available at zynq_pr_rd/sw/boot/linux.

Shortcut: A pre-generated Linux boot image is available at zynq_pr_rd/sd/linux/BOOT.bin.

7 Running the Reference Design in Hardware

This section describes how to set up the ZC702 board and additionally required hardware, create standalone and Linux SD-card images based on the provided reference design, boot up the device using SD boot mode, and finally run and operate the different software applications. The reference design supports two video resolutions: 1080p (default) and 720p at 60 frames per second. Note that the video input and video output resolutions need to match. Section 6.3 shows how to change the resolution of the standalone application; Section 7.3 shows how to change the video resolution in the Linux devicetree.

7.1 Setting up the ZC702 Evaluation Board

Refer to [2], Chapter 1 for kit contents and default jumper and switch settings. Reference design specific settings are described below:

7.2 Running the Standalone Software Application

The standalone SD-card image requires the following components:

BOOT.bin Standalone boot image (6.7)
sepia.bin Partial Sepia bitstreams (4.9)
sobel.bin Partial Sobel bitstreams (4.9)

Shortcut: A pre-built standalone SD-card image is available at zynq_pr_rd/sd/standalone.

7.3 Running the Linux Software Application(s)

The Linux SD-card image requires the following components:

BOOT.bin Linux boot image (6.8)
devicetree.dtb Device tree blob (5.2)
devicetree.dts Device tree source (5.2)
filter_cmd Linux command line application (6.4)
filter_qt Linux Qt application (6.5)
init.sh Setup script (5.3)
qt_lib.img Qt/Qwt libraries image file (6.5)
ramdisk8M.image.gz Linux root file system (5.3)
run_filter.sh Wrapper script (7.3)
sepia.bin Partial Sepia bitstreams (4.9)
sobel.bin Partial Sobel bitstreams (4.9)
zImage Linux kernel image (5.2)
zynq.png Zynq Qt splash screen image file (6.5)

Shortcut: A pre-built Linux SD-card image is available at zynq_pr_rd/sd/linux.

8 References

1. UG925, Zynq-7000 EPP ZC702 Base Targeted Reference Design
2. UG926, Zynq-7000 EPP ZC702 Evaluation Kit
3. UG873, Zynq-7000 EPP Concepts, Tools, and Techniques
4. UG821, Zynq-7000 EPP Software Developers Guide
5. UG744, Partial Reconfiguration of a Processor Peripheral Tutorial
6. XAPP890, Zynq All Programmable SoC Sobel Filter Implementation Using the Vivado HLS Tool
7. XAPP1159, Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC Devices
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