OSL SPI Aardvark

Connecting the Aardvark I2C/SPI Activity Board To The ML405

The SPI IP core was added to an ML405 reference design for this application. The SPI signals were pinned out to the daughter board connector on J6.

Connect pins on J3 and J6 of the ML405 to J5 of the Aardvark board as specified below using fly wires.

J3 3.3V Pin -> J5 +5V Pin
J6 GND Pin -> J5 GND Pin

J6 Pin 58 –> J5 SCK Pin
J6 Pin 60 –> J5 MOSI Pin
J6 Pin 62 –> J5 MISO Pin
J6 Pin 64 –> J5 SS Pin

3.3 volts is used from the ML405 while the EEPROM board expects 5 volts but it seems to run fine. 3.3 volts was used because is was used for I2C testing from the ML507 to this board with no problems.

The ground for the ML405 is the middle row of pins of the J3/J6 rows with the ground symbol at the bottom of the row. The pin in the middle row of the connector beside the 3.3V signal was used. Pins 58 - 64 of J6 are the outside row of pins.

No pullups were incorporated in the hardware design for the SPI bus signals.

A jumper was used on the SS Connect (J4) jumper of the EEPROM board.

MHS File Contents For The SPI Core

BEGIN xps_spi
PARAMETER INSTANCE = xps_spi_0
PARAMETER HW_VER = 2.00.b
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x84000fff
BUS_INTERFACE SPLB = plb
PORT IP2INTC_Irpt = xps_spi_0_IP2INTC_Irpt
PORT SS = xps_spi_0_SS
PORT MOSI = xps_spi_0_MOSI
PORT MISO = xps_spi_0_MISO
PORT SCK = xps_spi_0_SCK
PORT SPISEL = net_vcc
END

UCF Constraints

#### Module SPI_FLASH constraints

Net fpga_0_SCK_pin LOC=AB17;
Net fpga_0_SCK_pin IOSTANDARD = LVCMOS33;
Net fpga_0_MOSI_pin LOC=AB16;
Net fpga_0_MOSI_pin IOSTANDARD = LVCMOS33;
Net fpga_0_MISO_pin LOC=AB15;
Net fpga_0_MISO_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SS_pin<0> LOC=AA15;
Net fpga_0_SS_pin<0> IOSTANDARD = LVCMOS33;

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